`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 2022/06/25 22:41:06
// Design Name: 
// Module Name: branchcomp
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module branchcomp(
    input rst,
    input [1:0] branch,
    input [31:0] branch_a,
    input [31:0] branch_b,
    output reg [1:0] branch_res
    );
    
integer a,b;    
    
always @(*)
begin
    if (rst)
    begin
        branch_res <= 2'bzz;
    end
    else
    begin
        if (branch == 2'b01)
        begin
            a = branch_a;
            b = branch_b;
            branch_res <= (a == b)? `EQ: 
                          (a >  b)? `GT: `LT; 
        end
        else if (branch == 2'b10)
        begin
            branch_res <= (branch_a == branch_b)? `EQ: 
                          (branch_a >  branch_b)? `GT: `LT;
        end
        else
        begin
            branch_res <= 2'b11;
        end    
    end
end   
    
endmodule
